This invention relates to a path delay allocation method applied to an electronic apparatus of physical hierarchical design so as to allocate path delay target times to paths extending between a plurality of levels in the physical hierarchy.
A layout of an electronic apparatus, such as, that including LSIs is frequently designed by calculating signal delay times beforehand on the basis of logic information and utilizing the result of calculation for placement and routing of the LSIs. For example, a method for attaining such a placement and routing procedure without path delay violation is described in IEEE Trans. on CAD, Vol. 8, 1989, pp. 860-874. According to this method, the concept called a slack representing the difference between the period of time required for a signal to reach a specific point from an input pin and the period of time required for the signal to reach an output pin from that point is used to provide the net with a slack for path delay and utilize this slack for the path delay so as to attain the placement and routing without any path delay violation. The proposed method is a design technique that can be applied to one level of physical hierarchy.
In a logic circuit, a signal route extending from a flip-flop to another flip-flop is called a path. The period of time required for a signal to propagate through this path is called a path delay. According to the timing of a clock signal applied to the starting flip-flop and the end flip-flop on each path, the maximum allowable value and the minimum allowable value of the path delay are determined. In the physical hierarchy, the path delay is required to satisfy these target values. This requirement is called the path delay requirement. This path delay requirement for the maximum allowable value will now be specifically described, by way of example.
In the case of physical design of an electronic apparatus, placement and routing of all of the components forming the apparatus must satisfy the path delay requirement described above.
However, with the increase in the scale of the electronic apparatus, it is necessary to divide the apparatus and constitute the physical hierarchy levels such as LSIs, modules and printed circuit boards. In the design of the apparatus too, the logic of the entire apparatus is first divided into a plurality of hierarchy levels to deal with the increase in the scale, and, in parallel with the division, hierarchical design of various components in each level is made. For example, a plurality of LSIs are mounted on a module. Placement and routing of these LSIs is frequently designed independently of and in parallel with each other.
Thus, in an electronic apparatus of hierarchical design, a path extending between a plurality of levels in the physical hierarchy exists necessarily. Such a path is part of one of the levels in the physical hierarchy. Although the path delay target time for the entire path was determined, the path delay target time for such a subdivided path was not yet determined.
Suppose that two LSIs are mounted on a module, and a path starting from within one of the LSIs passes through a route on the module to end at the other LSI. The placement and routing of these two LSIs was done hitherto independently of each other. Therefore, it was the prior art placement and routing procedure that a severe path delay target time which was, for example, 1/3 of the machine cycle was set for the subdivided paths in each LSI.
However, as a higher performance is more and more demanded for an electronic apparatus, it is difficult to obey such a severe target time requirement when the path delay requirement which is so severe as described above is uniformly imposed on the subdivided paths. Also, when such a severe path delay requirement is uniformly imposed on the subdivided paths, this severe requirement is wasteful when the number of gates belonging to the path is small, and there is a slack for path delay of the subdivided paths. That is, unless the path delay target time is set for each subdivided path, the desired effective physical hierarchy cannot be achieved.